Jesse Gross b880b76c43 laguna: wire the DFlash target side ... Add what a DFlash draft borrows from its target: the tapped layer outputs, the raw embedding lookup, and the undecorated lm_head projection. The laguna draft architecture (DFlashLagunaForCausalLM) is registered here, alongside the only wired target. Matched nvfp4 target+draft pairs, M5 Max, temp 0.8, repeat_penalty 1.1, adaptive depth; decode tok/s: prose code edit laguna-xs plain 139.4 139.7 137.3 DFlash 142.3 139.2 145.1 laguna-s plain 75.4 70.0 72.4 DFlash 74.6 80.8 115.3		2026-08-07 19:33:35 -07:00
..
cohere2_moe	mlxrunner: let each model declare the cache slots it needs	2026-08-07 19:33:35 -07:00
dflash	laguna: wire the DFlash target side	2026-08-07 19:33:35 -07:00
gemma3	mlxrunner: let each model declare the cache slots it needs	2026-08-07 19:33:35 -07:00
gemma4	mlxrunner: let each model declare the cache slots it needs	2026-08-07 19:33:35 -07:00
glm4_moe_lite	mlxrunner: let each model declare the cache slots it needs	2026-08-07 19:33:35 -07:00
laguna	laguna: wire the DFlash target side	2026-08-07 19:33:35 -07:00
llama	mlxrunner: let each model declare the cache slots it needs	2026-08-07 19:33:35 -07:00
nn	nn/recurrent: run the gated-delta step in one launch	2026-07-31 10:18:54 -07:00
qwen3	mlxrunner: let each model declare the cache slots it needs	2026-08-07 19:33:35 -07:00
qwen3_5	mlxrunner: let each model declare the cache slots it needs	2026-08-07 19:33:35 -07:00
qwen3_5_moe	MLX: add header vendoring and remove go build tag (#14642)	2026-03-09 17:24:45 -07:00